1. Field of the Invention
The present invention relates to FIFO (first-in, first-out) architecture, and particularly to an interleaved FIFO memory array with look ahead conditional decoder for PCI applications.
2. Discussion of the Related Art
It is known to decode a FIFO to selectively advance particular entries in a FIFO to an output. Using a four-way interleaving architecture for performing this task is also known. An example is shown schematically in FIG. 1. U.S. Pat. No. 5,663,910 to Ko et al. (hereinafter "Ko et al.") substantially discloses the FIFO architecture shown in FIG. 1 and described below.
The FIFO of FIG. 1 is represented schematically as four subarrays of four registers, wherein each register can store 32 bits of data. This schematic arrangement is conceptual. Physically, the array including four subarrays is a single FIFO comprising 16 registers, each having 32 bits. The four subarrays are distinguished conceptually by pointer manipulation.
Each of the four subarrays of four registers of the architecture of FIG. 1 is supplied to a (different) multiplexer to which two-bit signals are supplied (hereinafter "two-bit multiplexer"). Different two-bit signals supplied to each two-bit multiplexer control the selection of one of the four registers from the subarray associated with the two-bit multiplexer to be supplied as the output thereof. That is, the two-bit signal dictates from which one of the four registers that 32-bit information located at current pointer addresses of that register will be read and supplied to the two-bit multiplexer to be output therefrom.
Each of the four two-bit multiplexers is supplied to a fifth two bit multiplexer having four inputs, one for each of the four two-bit multiplexers from which the fifth two-bit multiplexer receives input data. A two-bit signal is applied to the fifth two-bit multiplexer to control from which one of the four input two-bit multiplexers information is to be currently and/or next received. The "four-way interleaving" component of the FIFO architecture of FIG. 1 is realized when both data and control signals are interleaved to achieve the task of decoding the FIFO and selectively advancing entries for each of four conceptual subarrays of registers via four separate data paths initiated through the four two-bit multiplexers each configured to receive data from one of the four subarrays.
Use of the fifth two-bit multiplexer for receiving input directly from each of the first four two-bit multiplexers configured to receive information from its associated one of the four FIFO stacks becomes problematic at sufficiently high processing speeds. In fact, the disclosure of Ko et al. only appears to contemplate input FIFOs capable of receiving an input data stream having a frequency of 100 Mhz. See col. 6, lines 11-13; col. 7, lines 27-28. Thus, the disclosure of Ko et al. only provides an architecture (see FIG. 1A) which allows an input data stream having a frequency of 100 Mhz to be de-interleaved and written into SRAM memory blocks. See col. 7, lines 33-35.
The fifth two-bit multiplexer of FIG. 1 is encumbered with the task of conceptually selecting one of sixteen, 32-bit wide registers. A problem is that the fifth multiplexer of FIG. 1, and as disclosed in Ko et al., does not hold information received by each of the first four two-bit multiplexers, e.g., for four clock cycles before outputting the information in turn. The fifth multiplexer merely serves conceptually as a sixteen to one multiplexer.
It is desired to have signals clocked out at each clock cycle. Moreover, it is desired to avoid the complications of using the fifth two-bit multiplexer of FIG. 1, with its wide data path, and its inherent associated delay.